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参考文献

[1]Xilinx,"7 Series FPGAs Configurable Logic Block User Guide",ug474(v1.7),2014.

[2]Xilinx,"7 Series FPGAs Memory Resources User Guide",ug473(v1.11),2014.

[3]Xilinx,"7 Series DSP48E1 Slice User Guide",ug479(v1.8),2014.

[4]Xilinx,"UltraScale Architecture Configurable Logic Block User Guide",ug574(v1.4),2015.

[5]Xilinx,"UltraScale Architecture Memory Resources User Guide",ug573(v1.3),2015.

[6]Xilinx,"UltraScale Architecture DSP Slice User Guide",ug579(v1.3),2015.

[7]Xilinx,"Vivado Design Suite User Guide Design Flows Overview",ug892(v2015.4),2015. YuX80sISWpfYM3U/O8lf7ie20oO2+KF8RFyq0gdn56M0skcGVfn62sOYZ2ml09sq

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