[1] BANERJEE U, UKYAB T S, CHANDRAKASAN A P.Sapphire: a configurable crypto-processor for post-quantum lattice-based protocols[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019, 2019: 17-61.
[2] ALKIM E, EVKAN H, LAHR N, et al.ISA extensions for finite field arithmetic accelerating kyber and newhope on RISC-V[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 2020(3): 219-242.
[3] FRITZMANN T, SIGL G, SEPÚLVEDA J.RISQ-V: Tightly coupled RISC-V accelerators for post-quantum cryptography[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 2020(4): 239-280.
[4] XIN G, HAN J, YIN T, et al.VPQC: a domain-specific vector processor for post-Quantum cryptography based on RISC-V architecture.IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(8): 2672-2684.
[5] BANERJEE U, PATHAK A, CHANDRAKASAN A P.An energy-efficient configurable lattice cryptography processor for the quantum-secure internet of things[C]//2019 IEEE International Solid-State Circuits Conference-(ISSCC), 17-21 February 2019, San Francisco, CA, USA: IEEE 2019: 46-48.
[6] XING Y, LI S.An efficient implementation of the newhope key exchange on FPGAs.IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(3): 866-878.
[7] ZHANG N, YANG B, CHEN C, et al.Highly efficient architecture of newhope-NIST on FPGA using low-complexity NTT/INTT[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 2020(2): 49-72.
[8] ZHU Y, WEI S, LIU L.A high-performance hardware implementation of saber based on karatsuba algorithm.Technical report[J].IACR Cryptol ePrint Arch, 2020, 2020: 1037.
[9] ROY S S, BASSO A.High-speed instruction-set coprocessor for lattice-based key encapsulation mechanism: saber in hardware[J].IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020, 2020(4): 443-466.
[10] MERA J M B, TURAN F, KARMAKAR A, et al.Compact domain-specific co-processor for accelerating module lattice-based key encapsulation mechanism[C]//2020 57th ACM/IEEE Design Automation Conference (DAC), 20-24 June 2020, San Francisco, CA, USA: IEEE, 2020: 1-6.